1. Field of the Invention
This invention relates to a pattern verification method, a pattern verification system, a mask manufacturing method and a semiconductor device manufacturing method to be used for manufacturing a semiconductor device, a liquid crystal display element or the like.
2. Description of the Related Art
The progress of semiconductor manufacturing technologies in recent years is very remarkable. Semiconductor devices with a minimal processing size of 0.18 μm are currently being manufactured. Such micronization has been made feasible by the advancement of micro pattern forming technologies including mask process technologies, photolithography technologies and etching technologies. In the era when large pattern sizes are common, the surface profile of the LSI pattern to be formed is drawn on a wafer as mask pattern and a mask pattern exactly the same as the first mask pattern is formed and transferred onto the wafer by means of a projection optical system so that a pattern substantially identical with the first mask pattern is formed on the wafer by etching the underlying layer. However, in the course of micronization of mask patterns, it has been increasingly difficult to form a pattern exactly the same as the first pattern in the pattern forming process to give rise to a problem that the final dimensions of the finished product to not exactly agree with those of the mask pattern.
Particularly, in the case of lithography and etching process that is essential to micro-processing, the dimensional precision of a pattern to be formed is significantly influenced by the layout environment of the patterns other than the pattern to be formed that are arranged around the pattern. Thus, the optical proximity correction (OPC) technique and the process proximity correction (PPC) technique (to be referred to as PPC technique hereinafter) of adding an auxiliary pattern to a mask pattern in advance have been reported with the aim of reducing the influence and forming a desired pattern with the intended dimensions after the micro-processing operation.
As the optical proximity correction (OPC) technique and the process proximity correction (PPC) technique have become more sophisticated than ever, it is currently not easy to predict the profile of the pattern to be finished on a wafer because of the large difference between the pattern designed by a designer and the mask pattern that is actually used at the time of exposure to light and hence it is necessary to verify the finished product by means of a lithography simulator. D. M. Newmark et al., “Large Area Optical Proximity Correction Using Pattern Based Correction”, SPIE Vol. 2322 (1994) 374, proposes a verification tool for comparing the edges of a desired pattern to be formed on a wafer and those of the pattern transferred by using the layout after OPC and checking if the difference is found within a predetermined allowable range or not.
Japanese Patent Application Laid-Open No. 9-319067 proposes a technique for highly precisely predicting the positional displacement between the edges of a desired pattern and those of the corresponding transferred pattern by preparing physical models for proximity correction and verification. According to this proposal, a means for dissolving the problem of consuming a vast amount of time for verification at the full chip level of the device is also provided. More specifically, the above cited patent document proposes a verification technique realized by combining a rule-based correction technique of conducting corrections according to predetermined correction rules and a simulation-based correction technique of using a simulator for preparing models of phenomena that appear as a result of the exposure/development process.
To date, it has been possible to output the results of a transfer simulation realized by repeating the operation of optical proximity correction (OPC) and using the layout of the finished mask and that of the mask obtained as a result of the repeated OPC operation. However, the obtained information does not contain information that tells the designer about how to draw the layout.
Additionally, with the known verification processes using a lithography simulator, it is necessary to compute the light intensity at many evaluation points to make them very time-consuming ones. Therefore, there is a strong demand for a verification process that can improve the turnaround time (TAT) of the flow of the verification process.
Meanwhile, patterns on wafers are accompanied by problems that can roughly be classified into two types. One is that the obtained pattern shows discrepancies from the desired pattern regardless of the conditions under which the transfer operation is conducted and the other is that the obtained pattern does not give rise to any problem under “ideal” conditions but shows discrepancies once the process conditions change.
However, it is not possible to discriminate the above two types of problems for the produced pattern because what is output by any of the known techniques is the data obtained by comparing the produced pattern with the desired pattern, or the “ideal” pattern.
As discussed above, to date, while it has been possible to output the results of verification of the desired pattern and the mask pattern, it has not been possible to provide the designer with a guideline when the mask pattern requires to be modified. Additionally, it is desired to improve the TAT of the flow or the verification process. Still additionally, while it has been possible to compare the desired pattern and the mask pattern, it has not been possible to tell if the problem, if any, of a pattern is attributable to the desired pattern or to the process conditions.